In digital communications networks, it is common practice to transmit a binary data stream without explicitly transmitting a corresponding clocking signal. In such instances, a clock signal must be recovered from the data stream itself. One method of achieving this is to detect edge transitions between data bits and input this information to a phase-locked tracking loop (PLL) which then generates the desired clock.
Such a timing recovery circuit consists of an edge detector, a phase detector and a numerically-controlled oscillator (NCO). The NCO runs at a sample rate that is an integer multiple of the clock rate of the data itself which determines the precision with which the recovered clock can be produced. The basic functioning of this circuit is well-known to those skilled in the art. However, prior to the present invention, such clock recovery circuits have not been fully digitally implemented.